CYCP5=0, CYCP2=0, PLSP=0, CYCN3=0, CYCP3=0, CYCN5=0, CYCP4=0, CYCN1=0, CYCN2=0, CYCP1=0, CYCP0=0, CYCN0=0, CYCN4=0, PLSN=0
ELC Output/IPLS Interrupt Permission Automatic Clearing Register
CYCP0 | ELIPPR.CYCP0 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 0. |
CYCP1 | ELIPPR.CYCP1 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 1. |
CYCP2 | ELIPPR.CYCP2 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 2. |
CYCP3 | ELIPPR.CYCP3 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 3. |
CYCP4 | ELIPPR.CYCP4 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 4. |
CYCP5 | ELIPPR.CYCP5 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. 1 (1): Enables automatic clearing of the enable bit for the output of rising edges of pulse output timer 5. |
CYCN0 | ELIPPR.CYCN0 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 0. |
CYCN1 | ELIPPR.CYCN1 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 1. |
CYCN2 | ELIPPR.CYCN2 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 2. |
CYCN3 | ELIPPR.CYCN3 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 3. |
CYCN4 | ELIPPR.CYCN4 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 4. |
CYCN5 | ELIPPR.CYCN5 Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. 1 (1): Enables automatic clearing of the enable bit for the output of falling edges of pulse output timer 5. |
PLSP | ELIPPR.PLSP Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. 1 (1): Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. |
PLSN | ELIPPR.PLSN Bit Automatic Clearing 0 (0): Disables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. 1 (1): Enables automatic clearing of the enable bit for IPLS interrupt requests in response to detection of rising edges of the pulse output timer. |